Traditionally, in order to support the development of a program, there has been a technique for estimating a performance value such as an execution time of the program when the program is executed on a processor. For example, an actual host processor converts a code executable by a processor to be evaluated into a code executable by the host processor. Then, the host processor executes the code after the conversion and thereby simulates an operation when the processor to be evaluated executes the code. By simulating the operation, the host processor estimates a performance value of the code. For example, when an instruction to access a main memory, such as a load instruction or a store instruction, is executed, the processor to be evaluated accesses the main memory through a cache memory and thus a performance value varies depending on whether the access to the cache memory causes a cache miss or a cache hit. Traditionally, the cache miss or the cache hit is treated as a prediction result, and a performance value for the prediction result is treated as a performance value of the access instruction. There is a technique for correcting, when the host processor executes the access instruction after conversion, the performance value of the access instruction by simulating an operation of the modeled cache memory, based on whether the result of the execution is different from the prediction result (refer to, for example, Japanese Laid-open Patent Publication No. 2013-84178).
In addition, a cycle simulation that is executed to synchronize cycles of multiple execution blocks and simulate the execution blocks in parallel is known (refer to, for example, Japanese Laid-open Patent Publication No. 2007-207158). Furthermore, a technique for detecting a potential failure of programs to be executed in parallel when simulating operations of multiple central processing units (CPUs) and a hardware resource shared by the multiple CPUs is known (refer to, for example, Japanese Laid-open Patent Publication No. 2011-203803).
However, if a processor to be evaluated has multiple cores, a cache memory is shared by the cores, and destinations to be accessed in accordance with access instructions executed by the cores are the same or close to each other, a cache hit and a cache miss cause different results, depending on the order of the access. In this case, in the conventional techniques, a performance value is calculated for each of the cores, and the accuracy of calculating performance values of programs is reduced.
According to an aspect, an object of the disclosure is to provide a calculating device, a calculation method, and a calculation program that may improve the accuracy of calculating performance values of programs.